The ever-expanding capabilities of low-cost consumer chips have grown to encompass digital video processing. As a sexy application that creates cool demos, digital video has been adopted by a plethora of chip and semiconductor intellectual property startups. The market for digital video processors has become supersaturated with vendors contending for a limited number of sockets in the next generation of "killer" consumer products. 2007 will bring about a turning point in this fledgling market as we enter a period of closings and consolidation. Vendors must compete for sockets on the key metrics of cost, power consumption, and programmability.
Unlike the MHz, MIPS, and FLOPS races of yesteryear's general-purpose processors, because video coding and transmission are well standardized, performance beyond the ability to decode standards is a secondary consideration for video processors. However, die size, its effect on chip cost, and its effect on the BOM cost of consumer products remains a paramount concern. Likewise, in the design of chips for the growing market of battery-powered mobile devices, low power consumption is also critical.
The first digital video processors for consumer devices were hardwired for single video coding standards. This was necessary to fit within cost and power budgets because hardwired processors employ transistors more efficiently than fully programmable processors. As instruction sets were honed for digital video processing it became practical and as more video coding standards were developed it became advantageous to use software programmable video processors.
Many important factors distinguish programmable media processors. A mature architecture has better development tools and a supporting "ecosystem". RISC-based embedded media processors, configured with an MMU and SIMD instructions, can run full operating systems while handling audio, video, and stream synchronization, all real-time. Such processors are supported by mature compilers, which enable system designers to easily differentiate their products through software design.
Best software performance is achieved on any processor when a software engineer optimizes inner loops. Interconnected RISC processor cores and SIMD media engines are easier to optimize at low-levels than wide VLIWs because a RISC processor's programming model is linear and more easily modified than the execution-unit-parallel programming of VLIW architectures. Furthermore, requiring full long instruction words for pieces of software that can not take advantage of parallelism reduces cache store efficiency and wastes significant silicon area in today's chips that contain large percentages of SRAM for on-chip caches.
At a higher level, a multi-core interconnection of RISCs and SIMD media engines more naturally approximates the data flow pipeline of multimedia algorithms than the lock-step operation of wide parallel ALUs found in VLIWs. Today's RISC vs VLIW architecture battle is like yesteryear's x86 vs RISC architecture battle except that this time RISCs have the ecosystem advantage.
In 2007 and beyond we can expect a shift in video processors toward software programmable, RISC-based, SIMD-enhanced designs. These processors, with good silicon efficiency, multi-core scalability, and a large ecosystem of video, audio, and operating systems will have the advantage.
Jonah Probell is Director of Multimedia Solutions for ARC International and the author and editor of the web site VideoBits.ORG.
© Copyright 2007 Jonah Probell